1. Field of the Invention
The present invention relates to an input/output (I/O) protective device that protects an internal circuit in a semiconductor device from external noise such as a surge and the static electricity, and more particularly to an input/output protective device capable to provide a protection even against high voltage external noise having rapid rising characteristics.
2. Description of the Related Art
A semiconductor device, in general, comprises an internal circuit to realize a prescribed function, a pad that is connected to this internal circuit and used for input and output of signals and a lead terminal being connected to this pad. This lead terminal is then connected with an electric circuit outside, when required. An input/output protective device for a semiconductor device is set between the internal circuit and the pad for input/output, and if external noise such as a surge and the static electricity is applied to the lead terminal, the input/output protective device prevents such external noise to degrade the internal circuit therein by inducing an electric discharge in a protective element that comprises a transistor, a diode or the like.
For instance, in JP-A-3-248567, there is disclosed a structure in which aluminum wiring 31 of a drain node and a source node are, respectively, connected to a conductive layer 36 through contacts 33 and this conductive layer 36 is connected to a diffusion layer 34 through a contact 35 having an elongated contact hole, as shown in FIG. 8. When external noise such as a surge is applied thereto, this structure prevents the electric field centralization on a certain region of the diffusion layer 34 from developing and, thus, a contact therein from being degraded.
Further, JP-B-8-24183 discloses that, in a semiconductor device that has, as shown in FIG. 9, a first diffusion region 46 and a second diffusion region 48, both of which are substantially rectangular in shape and formed in an element region isolated by a field oxide film 42, sandwiching a gate electrode 42, and contact apertures 41 and 47 disposed in these first and second diffusion regions, the electric field centralization is liable to develop on a boundary point 43 in a corner section of the first diffusion region 46 on the gate electrode side, which easily leads to the generation of the electrostatic stress. For the purpose of overcoming this problem, the invention in said publication discloses a structure, wherein recess sections 45 are set in each corner section of the first diffusion region 46 on the opposite side to the gate electrode 44 and formed in such a way that the ratio of the length L of the side of said recess section which is substantially parallel to the boundary line between the first diffusion region 46 and the gate electrode 44 to the distance d from this side to the gate electrode is 1.5 or more. In this instance, setting recess sections 45 in the first diffusion region 46 lengthens the path from a contact aperture 41 to the boundary point 43 and increases the diffusion resistance, and thereby the electric field centralization on the boundary point can be made to relax.
With respect to such an input/output protective device, the protective ability thereof has been, hitherto, evaluated by the machine model method (referred to as the MM method, hereinafter), the human body method (referred to as the HBM method, hereinafter) or the like. The standard of the actual test method for the MM method is being defined by the Electronic Industries Association of Japan (referred to as EIAJ, hereinafter) and, in the U.S., by the EOS/ESD Association. The MM method in conformity with the EIAJ is referred to as the EIAJ method, and the MM method in conformity with the EOS/ESD Association, as the EOS/ESD method, hereinafter.
FIG. 6(a) illustrates the set-up of a test device. In the test method for the MM method, a capacitor C0 with a capacitance of 200 pF is charged to a prescribed test voltage and electrostatic discharge is applied to a lead terminal (not shown in the drawing) connected with a pad 53 of a semiconductor device 100, and then the evaluation of the voltage level to cause the breakdown of the semiconductor device is made. In practice, a test operator first applies a voltage of 50 V to a capacitor C0 as a test voltage and then turns on a switch SW, actuating the electrostatic discharge which is applied to a protective element 101 through a lead terminal and a pad 53 in each semiconductor device 100. After that, using a tester (not shown in the drawing), the test operator carries out the function test for the semiconductor devices 100 to find out whether each semiconductor device 100 can operate normally or not, and counts the number of degraded semiconductor devices 100. Subsequently, the test operator performs similar tests at a number of test voltages increased every 50 V and repeats Lt counting the number of degraded semiconductor devices 100 each time.
FIG. 6(a) shows a simulation model of the test according to the MM method for obtaining the waveform of a current flowing through the protective element 101 in the semiconductor device 100 by means of calculation, while FIG. 6(b) shows a plan view of the semiconductor device 100. The simulation model shown in FIG. 6(a) is composed of a test device 200 and the semiconductor device 100 to be tested. The test device 200 consists of a capacitor C0 with a capacitance of 200 pF that is to be charged to a test voltage and a parasitic inductor L, a parasitic resistor R and a parasitic capacitor C of the test device 200 as well as a switch SW to apply the test voltage to the semiconductor device 100.
The semiconductor device comprises a protective element formed on a P-type substrate 51, a pad 53 connected thereto and a lead terminal (not shown in the drawing) connected thereto. The protective element 101 has two N+-diffusion layers 52a and 52b and these N+-diffusion layers 52a and 52b are disposed at a given space, facing each other. Between the N+-diffusion layers 52a and 52b, the P-type substrate 51 is present so that the protective element 101 shown in FIG. 6 forms an NPN parasitic transistor. An insulating film 54 is formed over the N+-diffusion layers 52a and 52b, and metal wirings 55a and 55b are formed thereon. The metal wirings 55a and 55b are connected through contacts 56a-56e and 57a-57e to the N30-diffusion layers 52a and 52b, respectively. Further, the N+-diffusion layer 52a is connected through the metal wiring 55a and the pad 53 to the lead terminal (not shown in the drawing), while the N+-diffusion layer 52b is connected through the metal wiring 55b and a contact 58 to the P-type substrate 51 and consequently to the ground.
Using the device simulator for the semiconductor device 100, the present inventors conducted simulation with the equivalent circuit shown in FIG. 6 to find out what effects these evaluation test methods, EIAJ method and EOS/ESD method, have on the actual protective element 101, respectively.
In the test device 200 shown in FIG. 6(a), for the EIAJ method, the parasitic capacitor C had a capacitance of 20 pF, the parasitic inductor L, an inductance of 10 xcexcH and the parasitic resistor R, a resistance of 10xcexa9, while, for the EOS/ESD method, the parasitic capacitor C had a capacitance of 7 pF, the parasitic inductor L, an inductance of 0.5 xcexcH and the parasitic resistor R, a resistance of 10xcexa9. Further, in the calculation, the test voltage to charge the capacitor C0 with a capacitance of 200 pF was taken to be 50 V.
FIGS. 7(a) and (b) show the results of the simulation when the test voltage was applied, for the EIAJ method and the EOS/ESD method, respectively. In these graphs, the value of the current flowing the test device 200 to the protective element 101 in the semiconductor device 100 is plotted in vertical axis, and the elapsed time after the switch SW was turned on is plotted in horizontal axis.
As shown in FIGS. 7(a) and (b), in the EIAJ method, the peak value of the discharge current is small but the time period for which the discharge current flows into the protective element is considerably long, while, in the EOS/ESD method, the time period for which the discharge current flows is short but the peak value of the discharge current flowing into the protective element is four or more times that in the EIAJ method.
This demonstrates that, although it was, hitherto, sufficient for the protective element to withstand the test voltage of 200 V in the EIAJ method, the performance criteria that the protective element is required to satisfy is recently being heightened. That is, the protective element is asked for, not only to satisfy the performance criteria set for the test in the EIAJ method but also to have a withstand voltage of 200 V of more in the testing of the EOS/ESD method.
The evaluation and examination of the results of the above simulation by the present inventors indicated that contacts 56a and 56e situated at the outermost sections of the N+-diffusion layer 52a which constituted the protective element 101 were destroyed in the EOS/ESD method. The reason for this is thought to be as follows.
As in the EIAJ method, when a positive high-voltage pulse having a relatively slow rising characteristic is applied to the pad 53, electric charges of this pulse are transferred to the parasitic NPN transistor which constitutes the protective element 101 and the breakdown takes place initially at the PN junction between the N+-diffusion layer 52a and the P-type substrate 51. The corner sections 59 (FIG. 6(b)) of the N+-diffusion layer 52a are particularly liable to this breakdown. The breakdown at the corner sections 59 generates holes within the P-type substrate 51 and these holes raise the substrate potential locally. As the time passes, the breakdown regions spread towards the central section (in the vicinity of the contact 56c) of the N+-diffusion layer 52a, which raises the potential of the P-type substrate further and causes the parasitic NPN transistor to start operating. Accordingly, in the case that a positive high-voltage pulse having a relatively slow rising characteristic is applied, an almost equal amount of the currents flow into every contact and no destruction of the internal circuit occurs.
However, when a positive high-voltage pulse having a rapid rising characteristic is applied, as in the EOS/ESD method, although the breakdown take place initially around the corner sections 59 of the N+-diffusion layer 52a in the same way as mentioned above, discharge currents are thought to flow locally to the opposite N+-diffusion layer 52b before the breakdown regions spread towards the central section (in the vicinity of the contact 56c) of the N+-diffusion layer 52a. Therefore, large currents flow into contacts 56a and 56e at the end sections that are adjacent to the corner sections 59 of the N+-diffusion layer 52a. The currents flowing out from contacts 56a and 56e then flow into contacts 57a and 57e at the end sections of the opposite N+-diffusion layer 52b, respectively, so that large currents tend to converge into contacts 57a and 57e at the end sections on the side of the opposite electrode, as well. This brings about the destruction of the contacts 56a, 56e, 57a and 57e at the end sections. As a result, the protective element 101 presumably becomes incapable to make the external noise induce a sufficient electric discharge and a high voltage becomes applied to the internal circuit, which brings about the destruction of the internal circuit.
Accordingly, for the EOS/ESD method wherein a large current flows for a short time, even if a diffusion layer 34 is connected through a conductive layer 36 as in the prior art shown in the afore-mentioned FIG. 8, the discharge current flows down through a contact 33a at the end section directly into the underlying diffusion layer 34 without waiting for the charges to spread over the entire conductive layer 36 uniformly. Therefore, that part of the diffusion layer 34 or the contact 33a itself is easily destroyed, indicating that the protection of the internal circuit given thereby is, in fact, insufficient.
Further, with respect to the prior art shown in FIG. 9, although there is provided a protection against the electrostatic breakdown at the boundary point 43 of the first diffusion layer 46 on the side of the gate electrode 44, there is provided no protection against the destruction of the contact section 41 whatsoever. Furthermore, because securing the distance d to the gate electrode as well as recess sections 45 is an essential condition for this prior art, the area of the protective element becomes substantially large, which becomes the primary cause to increase the chip area.
An object of the present invention is to provide an excellent input/output protective device capable to protect the internal circuit even when external high-voltage noise having a rapid rising characteristic is applied.
In light of the above problems, the present inventors conducted an investigation and found out successively that the above problems can be overcome by providing a means to abate, at least, a large current flowing rapidly into contacts disposed on the side of the input/output section.
Accordingly, the present invention relates to an input/output protective device having a protective element that prevents external high-voltage noise from entering the internal circuit by inducing an electric discharge between diffusion layers which are disposed on a semiconductor substrate and facing each other; wherein:
there are equipped with a plurality of contacts each of which connects a metal wiring layer with a diffusion layer; and
a contact at the end section of the protective element on the side of the input section, at least, is provided with a means to increase the resistance thereof so as to make that larger than the resistance of the other contacts.
The present invention also relates to an input/output protective device in which a first diffusion layer connected to an input/output terminal and a second diffusion layer connected to a ground or supply potential or to a wiring fixed at a predetermined potential are arranged as facing each other on a surface of a semiconductor substrate, wherein the device comprises a number of contacts for connecting wiring layers to the diffusion layers, and the length of the first diffusion layer is larger at the both end section than the length of the second diffusion layer by at least one contact pitch length.
In the present invention, a contact connecting a wiring with a diffusion layer at the end section on the side of the input/output, at least, is provided with a means to increase the resistance thereof, and thereby, even when a rapidly rising pulse is applied, the discharge current does not converge to the contact at the end section to which the preventive arrangement is given so that the destruction of the contact at the end section does not occur. Accordingly, the present invention enables to provide an excellent input/output protective device with a higher withstand voltage than the conventional ones, contributing a good deal to enhance reliability of the semiconductor device.